User Interfaces Ic Compiler Computer Science Essay

UIs Ic Compiler Computer Science Essay IC Compiler is the product bundle from Synopsys for Physical Design of ASIC. It gives important devices to finish the back end structure of the profound submicron plans. The contributions to the IC Compiler are: a door level netlist which can be from DC Compiler or outsider apparatuses, a point by point floorplan which can be from past Design Planning through IC Compiler or other outsider devices, timing imperatives and different limitations, physical and timing libraries gave by maker, and foundry-process information. IC Compiler produces a GDSII-design record as yield prepared for tape out of the chip. Furthermore, it is conceivable to send out a Design Exchange Format (DEF) document of set netlist information prepared for an outsider switch. IC Compiler utilizes a paired Synopsys Milkyway database, which can be utilized by different Synopsys devices dependent on Milkyway. [16] 4.2 User Interfaces IC Compiler can be utilized either with Shell interface (icc_shell) or with Graphical UI (GUI). Shell interface is the order line interface, which is utilized for cluster mode, contents, composing orders, and press button sort of activities. Graphical UI (GUI) is a progressed graphical investigation and physical altering apparatus. Certain assignments, for example, precisely showing the plan and giving visual investigation apparatuses, can just performed from the GUI. Additionally device order language (Tcl), which is utilized in numerous applications in the EDA business, is accessible to IC Compiler. Utilizing Tcl, you can compose reusable methodology and contents. The IC Compiler configuration stream is a simple to-utilize, single-pass stream that gives focalized timing conclusion. Figure 4.1 shows the fundamental IC Compiler configuration stream, which is based on three center orders that perform situation and streamlining (place_opt), clock tree combination and enhancement (clock_opt), and steering and postroute advancement (route_opt). [16] icc1 Figure 4.1 IC Compiler Design Flow [21] For most structures, if the place_opt, clock_opt, and route_opt steps are followed, IC Compiler will give ideal outcomes. You can utilize IC Compiler to effectively perform chip-level structure arranging, situation, clock tree amalgamation and steering on plans with moderate planning and blockage challenges. To additionally improve the nature of results for your plan you can utilize extra orders and switches for position, clock tree union, and steering steps that IC Compiler gives. IC Compiler configuration stream includes execution of following advances: 1. Set up and set up the libraries and the structure information. 2. Perform configuration arranging and force arranging. - Design arranging is to perform fundamental strides to make a floorplan, decide the size of the structure, make the limit and center zone, make site columns for the position of standard cells, set up the I/O cushions. - Power arranging, is to perform essential strides to make a force intend to meet the force financial plan and the objective spillage current. 3. Perform situation and improvement. IC Compiler situation and improvement utilizes upgraded position and blend advancements to create a legitimized arrangement for leaf cells and a streamlined structure, which locations and resolves timing conclusion issues for the gave plan. You can enhance this usefulness by improving for power, recuperating territory for arrangement, limiting clog, and limiting planning and configuration rule infringement. To perform arrangement and streamlining, utilize the place_opt center order (or from GUI pick Placement menu and afterward Core Placement and Optimization sub-menu). 4. Perform clock tree union and streamlining. To play out the clock tree union and streamlining stage, utilize the order clock_opt (or pick Clock > Core Clock Tree Synthesis and Optimization in the GUI). IC Compiler clock tree union and implanted improvement tackle convoluted clock tree blend issues, for example, blockage shirking and the connection among's preroute and postroute information. Clock tree advancement improves both clock slant and clock inclusion delay by performing cradle measuring, support migration, door estimating, entryway movement, level modification, reconfiguration, defer addition, sham burden inclusion, and adjusting of interclock delays. 5. Perform steering and postroute advancement. To perform steering and postroute advancement, utilize the route_opt center order (or pick Route > Core Routing and Optimization in the GUI). As a major aspect of steering and postroute streamlining, IC Compiler performs worldwide directing, detail steering, track task, topological improvement, and designing change request (ECO) steering. For most structures, the default steering and postroute advancement arrangement produces ideal outcomes. On the off chance that essential, you can enhance this usefulness by advancing directing examples and diminishing crosstalk or by altering the steering and postroute advancement capacities for extraordinary necessities. 6. Perform chip completing and structure for assembling errands. IC Compiler gives chip completing and plan to assembling and yield abilities that you can apply all through the different phases of the structure stream to address process configuration issues experienced during chip producing. 7. Spare the plan. Spare your plan in the Milkyway position. This organization is the inside database group utilized by IC Compiler to store all the coherent and physical data about a plan. [16] 4.3 How to Invoke the IC Compiler 1. Sign in to the UNIX condition with the client id and secret phrase . 2. Start IC Compiler from the UNIX promt: UNIX$ icc_shell The xterm unix brief transforms into the IC Compiler shell order brief. 3. Start the GUI. icc_shell> start_gui This window can show schematics and intelligent programs, in addition to other things, when a plan is stacked. 4.4 Preparing the Design IC Compiler utilizes a Milkyway plan library to store structure and its related library data. This segment portrays how to set up the libraries, make a Milkyway plan library, read your structure, and spare the plan in Milkyway group. These means are clarified in the accompanying areas: à ¢Ã¢â€š ¬Ã¢ ¢ Setting Up the Libraries à ¢Ã¢â€š ¬Ã¢ ¢ Setting Up the Power and Ground Nets à ¢Ã¢â€š ¬Ã¢ ¢ Reading the Design à ¢Ã¢â€š ¬Ã¢ ¢ Annotating the Physical Data à ¢Ã¢â€š ¬Ã¢ ¢ Preparing for Timing Analysis and RC Calculation à ¢Ã¢â€š ¬Ã¢ ¢ Saving the Design 4.4.1 Setting Up the Libraries IC Compiler requires both rationale libraries and physical libraries. The accompanying areas depict how to set up and approve these libraries. à ¢Ã¢â€š ¬Ã¢ ¢ Setting Up the Logic Libraries: IC Compiler utilizes rationale libraries to give timing and usefulness data to every single standard cell. What's more, rationale libraries can give timing data to hard macros, for example, RAMs. IC Compiler utilizes factors to characterize the rationale library settings. In every meeting, you should characterize the qualities for the accompanying factors (either intuitively, in the .synopsys_dc.setup record, or by reestablishing the qualities spared in the Milkyway structure library) with the goal that IC Compiler can get to the libraries: à ¢Ã¢â€š ¬Ã¢ ¢ search_path Records the ways where IC Compiler can find the rationale libraries. à ¢Ã¢â€š ¬Ã¢ ¢ target_library Records the rationale libraries that IC Compiler can use to perform physical improvement. à ¢Ã¢â€š ¬Ã¢ ¢ link_library Records the rationale libraries that IC Compiler can look to determine references. à ¢Ã¢â€š ¬Ã¢ ¢ Setting Up the Physical Libraries: IC Compiler utilizes Milkyway reference libraries and innovation (.tf) records to give physical library data. The Milkyway reference libraries contain physical data about the standard cells and large scale cells in your innovation library. Moreover, these reference libraries characterize the position unit tile. The innovation records give data, for example, the names and attributes (physical and electrical) for each metal layer, which are innovation explicit. The physical library data is put away in the Milkyway structure library. For every cell, the Milkyway plan library contains a few perspectives on the cell, which are utilized for various physical structure errands. On the off chance that you have not as of now made a Milkyway library for your structure (by utilizing another device that utilizes Milkyway), you have to make one by utilizing the IC Compiler apparatus. On the off chance that you as of now have a Milkyway structure library, you should open it before chipping away at your plan. This segment portrays how to play out the accompanying errands: à ¢Ã¢â€š ¬Ã¢ ¢ Create a Milkyway plan library To make a Milkyway plan library, utilize the create_mw_lib order (or pick File > Create Library in the GUI). à ¢Ã¢â€š ¬Ã¢ ¢ Open a Milkyway plan library To open a current Milkyway plan library, utilize the open_mw_lib order (or pick File > Open Library in the GUI). à ¢Ã¢â€š ¬Ã¢ ¢ Report on a Milkyway structure library To investigate the reference libraries connected to the plan library, utilize the - mw_reference_library choice. icc_shell>report_mw_lib-mw_reference_library design_library_name To investigate the units utilized in the plan library, utilize the report_units order. icc_shell> report_units à ¢Ã¢â€š ¬Ã¢ ¢ Change the physical library data To change the innovation record, utilize the set_mw_technology_file order (or pick Document > Set Technology File in the GUI) to indicate the new innovation record name and the name of the structure library. à ¢Ã¢â€š ¬Ã¢ ¢ Save the physical library data To spare the innovation or reference control data in a document for sometime in the future, utilize the write_mw_lib_files order (or pick File > Export > Write Library File in the GUI). In a solitary summon of the order, you can yield just one sort of document. To yield both an innovation record and a reference control document, you should run the order twice. à ¢Ã¢â€š ¬Ã¢ ¢ Verifying Library Consistency: Consistency between the rationale library and the physical library is basic to accomplishing great outcomes. Before you process your d